The worldwide semiconductor packaging market will grow about nearly eight per cent per year as more system in package and wafer level chip-scale packages ship – By James Carbone
Over the next five years semiconductor buyers can expect to purchase more integrated circuits housed in advanced semiconductor packages such as system in package, wafer level and 2.5D packages.
The growth of Internet of Things (IoT) applications, artificial intelligence (AI) and use of sophisticated electronics system in automobiles has resulted in greater use of the latest semiconductor packages, which can enhance performance of ICs and minimize cost in many instances. Of course, advanced packages will not totally replace older, traditional chip packages such as plastic quad flatpack (PQFP) , small outline integrated circuit (SOIC), dual inline plastic (DIP), ball grid array (BGA) and dozens of other mature packages because different packages are needed depending on the product and where it is used.
Jan Vardaman, president of TechSearch International, Inc., based in Austin, Teas, said semiconductor packages have proliferated over the years and “there is no one-size-fits-all solution, no single package” for every chip. The package that “you use for an IoT sensor in a benign environment is not the same package” that you can use in the harsh environment of an automobile, she said.
She added, packaging used to be an afterthought when a chip was designed, but today “it is no longer an afterthought. It’s front center.”
While the number of packages has proliferated, some are being used more than others. Demand for advanced packages will grow steadily and increase as a percentage of the overall semiconductor packaging market.
Worldwide semiconductor packaging revenue will rise from $26.1 billion in 2018 to about $41.1 billion by 2024 and will post 7.96 per cent compound annual growth rate during that time, according to researcher Mordor Intelligence. The dollar value of advanced chip packages will rise because electronics has proliferated into more end equipment and there has been transformation in terms of characteristics, integration and energy efficiency of products, which is impacting packaging development, the researcher said.
One package that will be in more demand is system in package (SiP). “SiP is gaining a lot of speed,” said Bob Johnson, research vice president at Gartner Inc. “The idea goes back to multichip modules in the 1980s and 90s. But what they’ve done now is they come up with innovative techniques that enable multiple die together in a single package, “he said.
Stacked or tiled?
System in package handles most, if not all the functions of an electronic system. With SiP, semiconductor die can be stacked vertically or tiled horizontally unlike multichip modules. A SiP can contain a processor, DRAM, flash memory, which are mounted on the same substrate. SiP is used in smart phones, music players, wearable electronics and IoT applications. SIP will also be used in healthcare applications and in so-called “smart” applications such as smart city, smart bike and smart automotive.
“The idea is you package multiple die from multiple functions in a single package. They’ve developed between chip interconnects that are actually processed like a wafer,” said Johnson. So, they have the real tight spacing that you can get on a wafer. They have low resistivity.”
A SiP contains six or eight separate “chiplets” and functions “together as a whole. Each piece can’t function separately. It has to be connected to the other things to work,” he said.
One example of SiP is an AMD microprocessor which is built on a 7nm process. The chip has four cores which have a lot of transistors and computing power. “Those cores are surrounded by a whole bunch of chips in the same package at 14nm to do things like the I/O drivers, memory management, and some cache memory,” said Johnson.
Besides AMD, Intel, TSMC, GlobalFoundries are focusing on SiP. The larger outsourced semiconductor assembly and test (OSAT) companies are using SiP, but the smaller OSATs don’t have the resources to make the necessary investment in the packaging technology.
“The difficulty with advanced packaging systems is that they rely on wafer level packaging technology, which requires a higher level of capital investment than regular packaging so only the larger OSATS can afford it,” said Johnson. Most OSATs don’t have the resources for the research and development in R&D to deliver the whole SiP solution, he said.
Apple is already using SiP in some of its products. “One of the early examples of a SiP package is the Apple Watch. “The original innards of an Apple Watch were one package,” Johnson said. ASE, the largest OSAT company in the world and based in Taiwan, developed and manufactured the one package, he said. More wearable electronics will use semiconductors in system in package, he said.
“Tremendous” growth seen
HiSilicon and QUALCOM are also looking into advanced packaging and other companies will follow suit. “SiP will grow tremendously” because it will reduce costs and improve performance,” said Johnson. Some performance increases can be achieved by putting some of the peripheral die directly on top of a microprocessor rather than next to it so there is shorter distance for the signal to travel.
With SiP, memory can be placed on top of the processor to reduce space and improve performance. “In some cases, you can put cache memory directly above the processor,” said Johnson. “It is actually closer to the processor than if it is next to it in the same chip.” When cache memory is closer to the processor, “you get better signal integrity going between the memory and the processor,” he said.
Demand is also growing for other advanced semiconductor packages such as flip-chip, wafer-level chip scale packaging and 2.5D packaging.
With flip-chip packages, chips are connected to a printed circuit board or another chip with solder bumps that have been placed onto chip pads during the final wafer processing step. To mount the semiconductor to external circuitry such as a board, it is flipped over so that its top side faces down and its pads align with matching pads on the external circuit. Solder is reflowed to complete the interconnect. This differs from wire bonding where wires are used to connect the chip pads to external circuitry.
Because of the proliferation of portable electronic equipment, wafer-level chip-scale packaging is in greater use as it enables chips to be placed in the smallest packages. It is a very thin package often used in smart phones.
With wafer-level packaging (WLP), an IC is packaged while still part of the wafer and the package is almost the same size of the die. The top and bottom outer layers of packaging are attached to the solder bumps to integrated circuits while still in the wafer. Packaging test and testing and burn-in are done at the wafer level. The wafer is then diced.
Wafer-level chip scale packaging (WL-CSP) is the smallest package on the market. A WL-CSP is a bare die with a redistribution layer to rearrange the contacts on the die so that they can be big enough and have sufficient spacing.
More 2.5D packages are shipping and are being used in such applications as network switches, router chips and graphics cards. With 2.5D packages, several chips are assembled side by side on a base called an interposer. The chips are manufactured separately and delivered to the assembly house in bare die.
Vardaman said while packages have advanced and become more sophisticated as semiconductors evolved, packages that were used 30 years ago are still in demand for some products. “We like to think of some packages going obsolete, but we’re still using TO packages for power devices and there’s increased demand for power devices,” she said.